The present invention relates to a semiconductor memory including an MFMIS transistor having a ferroelectric capacitor provided on a field effect transistor.
An MFMIS transistor having a ferroelectric capacitor provided on a field effect transistor has a Metal/Ferroelectric/Metal/Insulator/Semiconductor multi-layer structure and includes a field effect transistor formed on a semiconductor substrate and a ferroelectric capacitor formed above the field effect transistor with an insulating film sandwiched therebetween with the gate electrode of the field effect transistor electrically connected to the lower electrode of the ferroelectric capacitor.
A circuit configuration of a semiconductor memory including the MFMIS transistor having the aforementioned structure will now be described with reference to FIG. 2.
As shown in FIG. 2, the MFMIS transistor includes a field effect transistor 10 and a ferroelectric capacitor 20 provided above the field effect transistor 10. The field effect transistor 10 includes a p-type well region 11, a drain electrode 12, a source electrode 13 and a gate electrode 14, and the ferroelectric capacitor 20 includes a lower electrode 21, a ferroelectric film 22 and an upper electrode 23. The gate electrode 14 of the field effect transistor 10 is electrically connected to the lower electrode 21 of the ferroelectric capacitor 20 so that the gate electrode 14 of the field effect transistor 10 can work as a floating gate of the MFMIS transistor, and the upper electrode 23 of the ferroelectric capacitor 20 is connected to a control gate 24.
When a voltage positive or negative with respect to the well region 11 is applied to the control gate 24, the polarization direction of the ferroelectric film 22 turns downward or upward. Therefore, even when the control gate 24 is grounded thereafter, the floating gate 14 keeps a potential positive or negative with respect to the well region 11. In the case where the potential of the floating gate 14 is positive, the field effect transistor 10 is always in an on-sate as far as the potential of the floating gate 14 is higher than the threshold voltage of the field effect transistor 10. In the case where the potential of the floating gate 14 is negative, the field effect transistor 10 is always in an off-state regardless of the magnitude of the potential of the floating gate 14.
Therefore, the on-state and the off-state of the field effect transistor 10 are allowed to respectively correspond to a data xe2x80x9c1xe2x80x9d and a data xe2x80x9c0xe2x80x9d, so that the MFMIS transistor can store a binary data, and the binary data can be read any time by detecting change of a drain/source current of the field effect transistor 10.
Accordingly, in the semiconductor memory including the MFMIS transistor, the stored data can be kept even when the voltage applied to the gate electrode (floating gate) 14 of the field effect transistor is lowered to 0 V by shutting off the power.
In the conventional semiconductor memory, however, the time duration for storing a data is restricted to as short as approximately 15 hours.
Now, the cause of the restriction in the data storage time of the conventional semiconductor memory will be described.
FIG. 3 is a diagram of an equivalent circuit of the MFMIS transistor of FIG. 2 in a data storage state. In FIG. 3, COX indicates a capacitance value of the gate insulating film, Cf indicates a capacitance value of the ferroelectric film 22 and R indicates a resistance component generated by the resistance of the ferroelectric film 22.
The lower electrode 21 and the upper electrode 23 of the ferroelectric capacitor 20 are not completely insulated from each other but there is finite resistance of 1xc3x971010 xcexa9xc2x7cm2 at most therebetween.
The capacitance value COX of the gate insulating film of the field effect transistor 10 is approximately 0.5 xcexcF/cm2 when the gate insulating film is formed from a silicon oxide film with a thickness of 10 nm. Also, the capacitance value Cf of the ferroelectric film 22 of the ferroelectric capacitor 20 is approximately 5 xcexcF/cm2 when the ferroelectric film 22 has a thickness of 100 nm.
Accordingly, when the initial potential of the floating gate 14 is indicated by V0 and the potential of the floating gate 14 attained after t hours is indicated by V, the voltage V is represented as follows:
V=V0xc3x97exe2x88x92t/CRxe2x80x83xe2x80x83(1)
wherein CR is a time constant and C is combined capacitance of COX and Cf represented as follows:
C=COX+Cfxe2x80x83xe2x80x83(2)
Accordingly, the following relationship holds:
CR=(0.5+5)xc3x9710xe2x88x926xc3x971010=5.5xc3x97104 (seconds)xe2x89xa015 hours
In consideration of the future use of a semiconductor memory including an MFMIS transistor, however, the data storage time is desired to be approximately 10 years (xe2x89xa03xc3x97108 seconds).
Accordingly, an object of the invention is largely increasing the data storage time of a semiconductor memory including an MFMIS transistor as compared with that of the conventional semiconductor memory.
In order to achieve the object, the semiconductor memory of this invention comprises an MFMIS transistor including a field effect transistor and a ferroelectric capacitor formed above the field effect transistor, and the semiconductor memory has a characteristic that a value of ("sgr"xe2x88x92p) is substantially not changed with time in a relational expression, V=(d/xcex50)xc3x97("sgr"xe2x88x92p), which holds among a potential difference V between an upper electrode and a lower electrode, a surface density of charge "sgr" of a ferroelectric film, polarization charge p of the ferroelectric film, a thickness d of the ferroelectric film and a dielectric constant xcex50 of vacuum when a data is written in the MFMIS transistor and the ferroelectric film is in a polarized state.
In the semiconductor memory of this invention, since the value of ("sgr"xe2x88x92p) is substantially not changed with time in the relational expression, V=(d/xcex50)xc3x97("sgr"xe2x88x92p), the potential difference V between the upper electrode and the lower electrode is not changed with time. Accordingly, a data written in the MFMIS transistor can be read after a very long period of time such as approximately 10 years (xe2x89xa03xc3x97108 seconds).
In the semiconductor memory, the thickness d of the ferroelectric film is preferably set to a value larger than a mean free path of carriers present in the upper electrode or the lower electrode.
In this manner, a carrier present in the upper electrode or the lower electrode is definitely trapped by a trapping level before reaching the opposing electrode (the lower electrode or the upper electrode), and hence, the value of ("sgr"xe2x88x92p) is not substantially changed with time. Accordingly, the potential difference V between the upper electrode and the lower electrode is substantially constant, so that a data can be stored for a sufficiently long period of time.